The present invention relates to the structure of a semiconductor device, in which a tape-like insulating member provided thereon with a number of wiring patterns and a number of electrode pads is bonded on a metal plate, semiconductor elements are mounted on the metal plate, the wiring patterns are electrically connected to electrodes of the semiconductor devices, and solder bumps are connected as external terminals to the electrode pads; and, more particularly, to a semiconductor device which has excellent connection reliability for the external terminals and excellent productivity in manufacturing it.
Recently, while high integration of semiconductor devices and providing a number of pins on semiconductor devices have progressed, a technique has been put into practical use for significantly increasing the number of pins (number of terminals) by changing the arrangement of the external terminals of a semiconductor package from the conventional linear arrangement, using leads to a two-dimensional arrangement using metal bumps. One of the specific structures is disclosed in the U.S. Pat. No. 5,216,278, in which semiconductor elements are mounted on one side of a printed circuit board and metal bumps are arranged on the other side thereof. This structure is generally called a BGA (ball grid array).
In addition, a semiconductor device has been developed for which the semiconductor package is reduced in size to as close to the dimensions of semiconductor element as possible. Such a semiconductor device is called a CSP (chip size package or chip scale package). Conventional CSP technology is, as disclosed in Japanese Patent Application Laid-Open Publication No. 6-504408 (WO92/05582), to manufacture a semiconductor device in which insulating tape with wiring patterns and external terminals is mounted onto a circuit formed surface of a semiconductor element through a flexible material, thereby electrically connecting the wiring patterns to electrodes of a semiconductor element. In addition, Japanese Patent Application Laid-Open Publication No. 6-224259 discloses a structure in which semiconductor elements are mounted onto a ceramic substrate with through holes, electrodes are provided on the other side of the ceramic substrate, and the ceramic substrate is mounted onto a printed circuit board. Moreover, Japanese Patent Application Laid-Open Publication No. 6-302604 discloses a CSP of a structure in which metal wiring patterns are formed on the circuit formed surface of a semiconductor element, and the metal wiring patterns are provided with external terminals.
Still further, Japanese Patent Application Laid-Open Publication No. 8-88293 discloses a semiconductor device of a structure in which insulating tape with wiring patterns and solder bumps (external terminals) is placed around a semiconductor element, and the wiring patterns are electrically connected to electrodes of the semiconductor element.
Among the above prior arts, the semiconductor device described in Japanese Patent Application Laid-Open Publication No. 8-88293, that is, the semiconductor device with the insulating tape around the semiconductor element, is of a structure enabling it to simultaneously attain a reduction of the size and provision of multiple pins. Since this structure uses the insulating taper for wiring, the wiring pattern can be finer than a printed circuit board, so that the pitch between the solder bumps as the external terminals can be reduced, and the external dimensions of the package can be made small. In addition, since the solder bumps are provided outside the semiconductor element, a larger number of bumps can be provided regardless of the size of semiconductor element.
However, the semiconductor device with the conventional structure described above has the following points which it is desirable to improve.
The first point is the productivity. Since this structure uses insulating tape with low rigidity, it is necessary to bond a metal plate on the other side of the insulating tape in order to reinforce it. Unless the metal plate is bonded, the flatness of the tape cannot be maintained, and a step is formed at the tip of a solder bump, thereby significantly deteriorating connection reliability. If separate metal plates are prepared for each semiconductor element to assure the connection reliability and are bonded to the insulating tape, it significantly hinders the productivity.
The second point to be improved is the flatness of the insulating tape. When separate metal plates are prepared and bonded to the insulating tape, as described above, there is a possibility that the adhesive may not be maintained for uniform thickness, or warpage caused by the roll habit of the insulating tape may not be eliminated. If the insulating tape has poor flatness, dispersion may be generated in the height of the bumps, which are the external terminals, thereby degrading connection reliability.